View Single Post
·feist·
Member
(01-06-2012, 05:48 PM)
·feist·'s Avatar
http://forum.beyond3d.com/showpost.p...&postcount=166

Scaled comparison of Llano and Trinity, using the I/O pads on the left side for reference:



Some observations on the layout of the SIMD multi-processors -- the placement of the register file banks in the ALU array is different in Trinity, as well as the whole layout of the texture unit.

Here are the differences (so far) on the CPU side -- BD vs. Piledriver cores:



Those banks are most probably the pre-decode bits (used for the BTB, branch selector, end bits & etc.), that AMD has been using ever since the first K7 architecture to aid the instruction decode flow. And since these are located in the branch prediction area of the front-end block, I guess AMD is aiming at improving namely this aspect of the architecture.

For more on BTB and brand prediction, The Real World Technologies "AMD's Bulldozer Microarchitecture" article, found in the OP, covers it on page four.

http://www.realworldtech.com/page.cf...2610181333&p=4



edit:
http://forum.beyond3d.com/showpost.p...&postcount=177

This is comparison of the IGP "uncore" sections of Llano and Trinity -- SIMDs are cut out too. Trinity's section takes 40% more area, compared to Llano's.

Last edited by ·feist·; 04-09-2012 at 10:30 AM.