As it came up, I feel something needs clarifying:
The Wii U's CPU is not a modified Waternoose/Xenon.
We have a considerable number of sources pointing out that the CPU is capable of out of order execution. This isn't something you can just "add-in" to a chip, it requires a completely different instruction pipeline, and for all intents and purposes, the instruction pipeline is the CPU. All the other specs, like number of cores, cache size, etc. are superficial; a CPU is defined by the way it handles instructions, and the Wii U CPU handles instructions in a fundamentally different way than Xenon.
The CPU will be, by any reasonable criteria, a completely custom chip. The instruction pipeline is probably going to be very loosely based on the Power7's, and the AltiVec unit will probably be a heavily modified variant on the VSX, but it's a whole new CPU, and not a "modified" anything.