oversitting
Banned
40nm has about 6.2 million transistors per mm^2 from AMD.
If the Wii U's gpu is 156mm^2 with gpu + EDRAM and maybe additional IO.
http://www.realworldtech.com/iedm-2010/3/
says on 32nm EDRAM is >11Mbit/mm2, so we can assume it will about 1MB/mm2(8Mb/mm^2) on 40nm.
so ~32mm^2 will be used by the EDRAM.
this leaves 124mm^2 for the GPU and w/e else is there.
124*6.2= 768M transistors.
5670 with 627M transistors with 400SP. 4770 with 826M transistors has 640SP. 6670 with 716M transistors has 480SP.
So 400SP would be reasonable considering there would likely be some logic that goes with the EDRAM and some other IO and such.
400SP @ 550Mhz = 420 GFLOPs. Best case would be 480 SP = 500GFLOPs.
If the Wii U's gpu is 156mm^2 with gpu + EDRAM and maybe additional IO.
http://www.realworldtech.com/iedm-2010/3/
says on 32nm EDRAM is >11Mbit/mm2, so we can assume it will about 1MB/mm2(8Mb/mm^2) on 40nm.
so ~32mm^2 will be used by the EDRAM.
this leaves 124mm^2 for the GPU and w/e else is there.
124*6.2= 768M transistors.
5670 with 627M transistors with 400SP. 4770 with 826M transistors has 640SP. 6670 with 716M transistors has 480SP.
So 400SP would be reasonable considering there would likely be some logic that goes with the EDRAM and some other IO and such.
400SP @ 550Mhz = 420 GFLOPs. Best case would be 480 SP = 500GFLOPs.