Wow! Is this a jeff_rigby post in disguise? This is the horror of dilettanteism: an accumulation of facts with no integrated knowledge. I'll pick a few tiny things out here.
So shorter pipelines, bigger caches, more memory registers and issuing one extra instruction per cycle when a branch instruction is available is not relevant to argue than Espresso might do a better work clock for clock than the Jaguar in this kind of scenario? (AI code).
Can you imagine a game built around advected forces in a volumetric grid? A smoothed particle hydrodynamics solver?
I've personally done volumetric grids with forces associated at each box and I don't think this is any different than what Mario Galaxy did on the Wii.
Regarding the smoothed particle hydrodynamics solver, I've never done that and I don't know what it is (something particle related to calculate the physics of water, I presume) but until I see it applied in a game in a way it improves the experience besides making the water more realistic, I won't say if this is good or if it isn't.
Have you written any SIMD code on these platforms? You're aware of how paired-single works, vis a vis AVX ISA (though Lord knows all write-thinking men preferred VMX128 and the Cell ISA)?
No, I haven't worked on those consoles. Unlike you I don't need to fool anyone to defend my points. But why are you now referring to the SIMD capabilities of the Espresso, if we were talking specifically about branchy integer code?
You realize write-combined memory isn't some fantasy that doesn't exist on modern CPUs?
True for the write gatherer that I'm sure the Jaguar also has in an equivalent form. But a DMA to L1 cache? The Jaguar doesn't have that...
For now, instead of learning something useful from someone that's supposed to know a lot, the conversation has been:
- The Espresso may do quite well compared to the Jaguars in terms of integer-branchi code.
- You speak a lot but you know nothing. Have you ever programmed SIMD code on those CPUs?
It's obvious that besides programming, you're pretty invested in console wars and deviating the conversation to where it interests you.
I insist, what was wrong about the shorter pipelines, the 2+1 issued instructions and the bigger caches impacting positively a branchy code?
Come on, man. Put down the flag. It's killing you.
Hey mr. programmer (a programmer that can't distinguish between a branch instruction and a SIMD one), why don't you enlighten me in