I never it would be too big for it handle, i just said it will cause a large hit, which any cache flush will cause. There are no ways around it, coherent memory writes from GPGPU on the XBONE causes the entire cache to flushed to memory.
If the hit to eSRAM is so small why even bother having a cache? theres a good reason its there, and the coherent GPGPU writes in the XBONE invalidates and flushes the entire thing, L1, L2 and even the read only texture cache i am led to believe.
It would appear that outside of the eSRAM itself, Microsoft has done nothing about this issue.
It should be noted that GCN also suffers from the same fate, its not just the XBONE, its something you normally just deal with, its something you don't have to deal with on the PS4.
You seem to think your qualified to try and call me out on my qualifications, and you seem to comment rather rigorously on most technical threads, what are your qualifications to be making such comments may I ask?.
I'm not making any assumptions, unless you think that assuming a cache has a much higher bandwidth and lower latency then any offchip memory is a 'large' assumption.
Don't get me wrong, I
know I'm not qualified, but I have a sneaking suspicion that you aren't qualified enough to make such large assumptions, either. And I'm not trying to be disrespectful when I say this. I just think that if you're going to make such a major assumption, then at least there should be some reasonable background or experience on the particular subject to go hand in hand with such a claim. That said, I don't want to discourage you from saying your piece, as you have every right to say whatever, and I do love discussing this kind of stuff, but I'm not sure if what you said would exactly prove accurate if a more qualified person were able to assess the soundness of the argument, but we'll operate on the assumption regardless that you're right, although I still think saying it will be a "massive" hit is perhaps a bit much.
Now, obviously the GPU needs the caches. They all do. Not having them would be absolute suicide and destroy performance, so the caches aren't necessarily there because ESRAM isn't helpful enough. They are there because they must be, regardless of what design decision Microsoft or Sony opted for.
Also, the ESRAM is sure to be further out from the GPU's L1 and L2 and other caches, but it's definitely not
offchip memory. It's on chip, and is a very similar style of memory to what's used inside the GPU's L1 and L2 caches, only obviously not as fast. The DDR3 is the only off chip memory in the xbox one equation. And, hypothetically, since Microsoft put in place ESRAM residency control, so that developers have more control over which pieces of data can simply remain inside ESRAM (something I have confirmation they did) without ever having to be moved, why couldn't a dev take advantage of the still rather low latency ESRAM, and have the GPGPU operation take place from within the ESRAM without having to flush the GPU cache in the first place? And the ESRAM obviously has plenty more capacity to spare than the much smaller GPU caches, so perhaps that's a way they could handle things?
ESRAM residency control is one of the main DX11.x enhancements that Microsoft highlights in their development document for the Xbox One along with
Tiled Resources.
Enhanced support for multithreaded graphics operations.
Batched resource creation.
Improved texture format and swizzling support.
Well, one of the first thing you learn when learning to optimize code is to make more cache friendly code because cache misses are expensive. You don't have to be a game programmer to know this. It applies to all programs.
Oh, believe me, I know this. I certainly say it all the time around here regarding ESRAM and the dangers of cache misses, but I'm saying how does he know that Microsoft doesn't have a solution in place to deal with just that issue? There's another piece of on chip memory that's the same kind of memory as the GPU's caches, just not nearly as fast, but it's also quite low latency. Instead of flushing the cache, why not take advantage of the, by cache standards, some of the enormous amount of space inside the ESRAM to help perform the coherent writes? Microsoft's hot chips presentation did showcase that the ESRAM appears to have some access to coherent memory.
