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3nm on the way - PCGamer

N

Nhranaghacon

Banned
This is going to provide such a huge step up from current hardware it can not be understated.

And then the article goes on to do just that, the correct amount of stepping up this would ensure is 15-20x more complexity than anything available - particularly when ML is utilized to help the process along.

We are talking about, at 3nm - laying silicon at a level far below what the human eye can possibly see. Essentially moving around atom's to create molecular fabric waferchips.

www.pcgamer.com

TSMC confirms 3nm tech for 2022, could enable epic 80 billion transistor GPUs

But probably a bit later than 2022...
www.pcgamer.com www.pcgamer.com
Monster chip foundry TSMC has confirmed its 3nm production node is on track for full mass production in the second half of 2022, according to Chinese tech site ItHome (in Chinese). TSMC reckons its 3nm node will pack in somewhere north of 250 million transistors per square millimetre of silicon, making it at least two and half times more dense than Intel’s latest 10nm node. In theory, TSMC’s 3nm tech could enable a GPU three times more complex than AMD’s new Radeon RX 6000 Series chips.
Click to expand...
 
German Hops

German Hops

GAF's Nicest Lunch Thief
It will go down to single atom quantum state to flip bits after 3nm or even before. Not much matter left that small.
I'm betting the yield at 3nm is going to be horrendous. Someone is going to figure out a better way.

Necessity is the mother of invention.

Whoever figures it out first would stand to control the next stepping of technology for literally the planet.

btw, my penis is 8nm. :messenger_8ball:
 
ratburger

ratburger

Member
I recall reading a while back that the reticle limit will be halved at either 5nm or 3nm, so max chip size will also be halved. At 7nm, largest possible chip is around 800mm², at 5nm (or was it 3nm?), it'll be roughly 400mm². Half as big chip means half as many transistors, which I don't think the PCGamer article is taking into account.

EDIT: Found it.
Current EUV (0.33 NA) maximum exposure field size is 26mm x 33mm, so 858 mm².
High-NA EUV (0.55 NA) halves that to 26mm x 16.5mm, so 429 mm².
semiengineering.com

Multi-Patterning EUV Vs. High-NA EUV

Next-gen litho is important for scaling, but it's also expensive and potentially risky.
semiengineering.com semiengineering.com
 
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K

kikkis

Member
What's the price per wafer? IIRC going from 7nm to 5nm already had gargantuan increase per wafer costs at least based on some estimate.
 
German Hops

German Hops

GAF's Nicest Lunch Thief
Photo A - Fire ant head mm scale features

Photo B - Semiconductor grade Si wafer with contamination (dust) micron scale features

Photo C - Gold sputter resolution target for SEM 30 nm scale features


280916_LL.jpg


280917_LL.jpg


280918_LL.jpg
 
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Rikkori

Rikkori

Member
It's a nice headline but don't expect it to do much for actual components within the next 5 years. It's too expensive and even on 7nm if you pay attention you see it be underutilised in terms of design for the sake of yields & costs. These die shrinks really mean nothing for consumers anymore, any big wins will be down purely to design.
 
mitch1971

mitch1971

Member
This stuff blows my mind. It's like the size of space. 250 million per millimetre. Head exploding. There must be limit with this method though. So what is next....?
 
The Fuzz damn you!

The Fuzz damn you!

Gold Member
Nhranaghacon said:
We are talking about, at 3nm - laying silicon at a level far below what the human eye can possibly see. Essentially moving around atom's to create molecular fabric waferchips.
Click to expand...
What an odd metric. Given the limits of human vision, the smallest size "thing" we can see is ~0.05mm (or so a quick Google tells me), or 50,000nm. Even the 8086 had transistor features smaller than that -- we passed the point of "laying silicon at a level far below what the human eye can possibly see" a looong time ago.
 
ZywyPL

ZywyPL

Banned
ratburger said:
I recall reading a while back that the reticle limit will be halved at either 5nm or 3nm, so max chip size will also be halved. At 7nm, largest possible chip is around 800mm², at 5nm (or was it 3nm?), it'll be roughly 400mm². Half as big chip means half as many transistors, which I don't think the PCGamer article is taking into account.

EDIT: Found it.
Current EUV (0.33 NA) maximum exposure field size is 26mm x 33mm, so 858 mm².
High-NA EUV (0.55 NA) halves that to 26mm x 16.5mm, so 429 mm².
semiengineering.com

Multi-Patterning EUV Vs. High-NA EUV

Next-gen litho is important for scaling, but it's also expensive and potentially risky.
semiengineering.com semiengineering.com
Click to expand...


And that's exactly why everyone is looking into multi-chip and stacking technologies, all manufacturers already knwo they won;t be able to overcome the physical barriers. Intel made a video some time ago about their long-term roadmap:

 
CuNi

CuNi

Member
Afaik TSMC is still using finFET, while Intel and Samsung plan on swapping to GAAT around 2022/2023. TSMC only plays to go for GAAT around 2025. GAAT is supposed to give a huge density increase, so if we take all road maps and treat them as facts, TSMC might go from first to 3rd place just by missing out GAAT.
 
Kerotan

Kerotan

Member
Rikkori said:
It's a nice headline but don't expect it to do much for actual components within the next 5 years. It's too expensive and even on 7nm if you pay attention you see it be underutilised in terms of design for the sake of yields & costs. These die shrinks really mean nothing for consumers anymore, any big wins will be down purely to design.
Click to expand...
So PS6 3nm in 8 years time?
 
P

prinz_valium

Member
Vier said:
It won't happen anytime soon, or happen ever?
Click to expand...

I believe never.
Design costs skyrocket and wafer costs skyrocket, too.
Maybe the PS5, because they have just one SOC, so they only need one new design. They also need a much smaller console 4 years into the generation.
But for Microsoft I don't see it. You can't build the Series X and S much smaller and they would need to design 2 chips. They also have less overall volume.
 
CuNi

CuNi

Member
Reizo Ryuu said:
The hard physical limit would be atom size, so about..0.4nm?
But you already run into limits before that because of quantum effects.
So what's next? 🤷‍♂️
Click to expand...

Let's also not forget that 3nm isn't 3nm. It's just the name of the node. Most things like transistors, gates etc. Isn't close to that.
 
N

Nhranaghacon

Banned
The Fuzz damn you! said:
What an odd metric. Given the limits of human vision, the smallest size "thing" we can see is ~0.05mm (or so a quick Google tells me), or 50,000nm. Even the 8086 had transistor features smaller than that -- we passed the point of "laying silicon at a level far below what the human eye can possibly see" a looong time ago.
Click to expand...
From 7nm all the way down to 3.5 nanometers you still see a beam of light bouncing off the substrate and emitting around the plasma beam emitted in particular - even though what is actually in utilization can not be seen.


At 3 nanometers you see nothing.

And to the above post, 3nm typically means 3.5 nanometers. 3nm++ being 3.3 and below
 
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