It's not as good as a single 320-bit bus across the address range, absolutely, but for 16 GB of ram that was never an option. And there's no realistic situation in which it won't be better than a single 256-bit bus.
From an application perspective I do think there's a difference, even for a system where two pools of memory share a common address range. When moving between memory pools I believe (I read a lot, but actually do a lot less so forgive me if I'm wrong) that there can be wildly different costs for different parts of the system accessing different memory pool. For example, IIRC Cell's read from GPU DDR3 was incredibly, unbelievably slow, at something like 1/1000 of percent of actual memory pool bandwidth.
XSX handles such situations very gracefully compared to a split memory pool, with relatively small and manageable graduations in total effective bw depending upon access. It appears to be a pretty forgiving way of getting a worthwhile boost in effective bandwidth for a system that can only stretch to 16GB of ram. And you don't have to DMA between regions unless you got something wrong to begin with.
I can't think of any split memory pool console that would be as fast or handle being treated as one single pool as well as this.