Except for normal particulate and process defects, engineering would do HTOL tests in ovens at elevated temps to accelarate bath tub, automative also do cold tests but thats another story, also testing on ATE on die and chips at elevated temps.
For 7nm+ the critical layers around the FinFET will be using EUV Litho, likely 4 or 5 layers or so, so the variances will be tigher
DO you not thing this will have been engineered to death and back ?
Out of interest, when a chip fails on an ATE, do you think a chip manufacterer knows why ? Do you know whats involved in stripping layers and looking for a needle in a haystack ? LOL
Also its a poor attemp to attack Ps5 clock frequency, the real question is why is XSX at 1.8 Ghz ? Its been designed primarily as a 4 instance server, but MS dont seem to have optimised the design as a console. XSX is supposed to be wide, but still has 4 shader arrays....go figure.