It's 50% now? It was 33% in your last post. And yes, I do think the jump from 28nm to 16nm was the major driver in allowing them to hit higher clocks with Pascal.
Percentage depends on what you compare to what. And no, it wasn't just the jump in production process, as this alone would net them the same results AMD got between Tonga and Polaris which is +20% at best. Couple this with the fact that Maxwell has already increased clocks over Kepler on the same 28nm process while AMD hasn't really improved them since GCN1.
In any case this is beside the point. I'm specifically arguing that I don't think increased clock speeds were the primary driver behind Vega's jump in transistors count. Maxwell is actually a perfect example, with a notable clock speed jump over Kepler (plus a variety of other architectural improvements) with little to no increase in transistor count or die size.
You are arguing with what AMD said themselves then. The only other notable addition - and it seems to be mentioned alongside the measures taken for clocks increase - is the 45MB of on-die SRAM. Nothing else in Vega 10 warrants such an increase in transistor complexity.
Increasing maximum clock speeds and improving power efficiency are effectively the same thing, it's all about moving the power curve down and to the right, allowing them to hit the same clocks at lower voltages or higher clocks at the same voltages. The reason they're launching a 345W card is that they're ramming right up against the end of that power curve, releasing a card with a max OC of probably 1.7GHz with a stock clock of 1.67GHz.
No, it's not the same thing at all. You need to do completely unrelated things to increase clocks and lower the power consumption. In fact, these things are usually on the opposite sides of what can be done. Vega 10's power usage is way worse than that of Fiji when compared to NV's competition which clearly shows that their focus was solely on clocks and not power efficiency. The reason they are launching a 345W card is because they can't compete without pushing the chip outside of normal power ranges.
I would bet very good money that Vega at the same ALU count and clock speed is comfortably more power efficient than Polaris. In fact, I wouldn't be surprised to see Vega Nano draw less power than RX580 while significantly outperforming it. We may even see Vega Nano outperform the 1070 at a similar power draw (although almost certainly at a higher price).
So far nothing points to this, every benchmark we had puts Vega below not only Polaris but Fiji/Tonga as well in power efficiency. I also very much doubt that Vega Nano will be able to outperform 1070 at 150W - it will likely land between 580 and 1070.
That's precisely what I mean. Nvidia could have pushed up boost voltages on Pascal to ~1.1V for a bit of extra performance and said "to hell with power consumption", but they didn't need to. AMD have basically said "to hell with power consumption", at least with the liquid cooled Vega 64.
AMD has said that because they haven't spent any time on improving their power consumption in Vega and as a result GCN5 is unable to compete with Pascal on the same power.
I didn't say TBDR, I said TBR. As far as I'm aware all mobile GPUs these days use tile-based rasterisation of one form or another.
TBIR and TBDR are two completely different things. Tiled rendering can save more power because it avoids external memory accesses altogether. Tiled rasterization saves way less power because it avoids external memory accesses only during one specific rendering stage.
They've talked about front-end improvements, but I from what I've read they haven't gone into much detail (although I may have missed it), indicating that they were relatively minor revisions. We're still seeing a 64CU Vega GPU underperform older, narrower GPUs on a pure performance/GF metric, which suggests that there's still something up.
Well, it's still GCN, still with the same execution bubbles, same 4-tick cadence, same heavy state changes and large penalties on flushes. As I've said, it may certainly be possible that the wider the shader array is - the more often these are happening during execution thus lowering the chip's efficiency compared to a more narrow one. And, yeah, FE seems to have some rather minor changes like the addition of proprietary primitive shader type - but I don't think that FE is the reason for GCN's main inefficiencies. It was somewhat of an issue with geometry pre-Polaris but in GCN4/5 this was mostly solved to the point where it trades blows with Maxwell/Pascal now.
nvidia gimps non quadro cards via drivers for product segmentation
AMD gimps gaming Radeon cards in the exact same way. Hence the "Radeon Pro" drivers.
_/¯
