I think you're partially right, in that it's intended both as a framebuffer and as low-latency GPGPU memory.
In fact, that brings me to another thought I'd had. I've been of the opinion for a while that
this chip being manufactured in Fab 8 is the Wii U GPU, something which would imply that the eDRAM is on-die with the GPU, rather than on a separate die. If IBM is involved in manufacturing the GPU, there might be other implications, though. A few pages back, Matt talked about the Wii U's GPU having a "significant" increase in registers over the R700 series. More register memory would be a benefit to GPGPU functionality, but usually comes at the expense of added transistors, which means higher power usage, more heat and a larger, more expensive die.
But what if Nintendo has replaced the register memory (which I assume is usually SRAM) with eDRAM? IBM's eDRAM takes up roughly one third the transistors of SRAM, and has similar power and heat benefits. With it, they could double the available register memory, from 128 registers per thread to 256, while
decreasing the transistor count over the reference R700. Alongside the extremely low memory latency that would come with an on-die 32MB pool of eDRAM, and the 32nm manufacturing process, this would make for a GPU which is very GPGPU code friendly, while still consuming very little power, both things which Nintendo seems to be focussing on. It would also be an answer to the question posed a few pages back of "Why would Nintendo spend years modifying a R700 rather than just using something like an E6760?"