So a thought recently occurred to me regarding the supposed "enhancer" the Foxconn leaker talks about, and in particular that 12mm x 18mm chip being used in it. It's on the crackpot end of the spectrum, but I think I've firmly established my crackpot credentials in this thread already, so why not bring it up
My basic thought is, what if it's not a single 12x18mm die, but rather two smaller dies packaged closely together?
Bear with me on this. Last year
I noticed a tidbit in a blog report of one of TSMC's symposia which confirmed that Nvidia "has a part in production with a logic chip and a four-die HBM stack", using TSMC's InFO multi-die packaging. This doesn't make a lot of sense for a desktop GPU (they could achieve the same results at lower cost with GDDR5), but may make sense for a mobile part where high bandwidth is required but GDDR5 is ruled out due to power draw (or space).
What occurred to me is that HBM2 dies are typically packed so closely to the logic die that they could easily be mistaken for a single die to someone who wasn't looking very closely. Have a look at this photo of Nvidia's GP100 package, with one (huge) GPU die and four HBM2 dies:
There's almost no gap between the GPU and HBM dies, and this gap could conceivably be even smaller with InFO packaging. The interesting thing is the dimensions of HBM2 dies, which are 7.75 mm × 11.87 mm. That is, they're pretty much exactly the same length as the chip reported to be used in the "enhancer". A logic die measuring approximately 10mm x 12mm side-by-side with a HBM2 die would look a lot like a single 18mm x 12mm die unless you got very close, and so, in theory, it's possible that this could be what the leaker saw.
Of course, it presents a lot of questions. Most notably, what is this 10x12mm die? Is it a GPU or an SoC? Why does it also apparently have 4GB of (presumably) LPDDR4 attached? If it does attach to Switch, would developers actually have to manage three different 4GB pools of RAM? If the regular Switch SoC can get by with 25.6GB/s, would Nintendo really feel they need 10 times that for the "enhancer"?
I'd still bet on the "enhancer" chip being a standard GP106, and Nvidia's HBM2-sporting mobile chip being Xavier, but I thought it was worth mentioning, at the very least. The fact that the dimensions line up so well is interesting, but I can't think of what the 10x12 die would be or why it would need so much bandwidth compared to a (similarly sized) regular Switch SoC.