Here's something on the 256MB cell limitation:
"Rambus XDR Memory System: Limited to 4 Devices, or Not?
In the previous article, the memory capacity of the XDR memory system was described as follows:
In the XDR memory system, each channel can support a maximum of thirty-six devices connected to the same command and address bus. The data bus of each device connects to the memory controller through a set of bi-directional point-to-point connections. In the XDR memory system, address and command are sent on the address and command bus at a rate of 800 Mbits per second (Mbps), and the point to point interface operates at a datarate of 3.2 Gbps. Using DRAM devices with 16 bit wide data busses, each channel of XDR memory can sustain a maximum bandwidth of 102.4 Gbps (2 x 16 x 3.2), or 12.6 GB/s. The CELL processor can thus achieve a maximum bandwidth of 25.2 GB/s with a 2 channel, 4 device configuration.
The obvious advantage of the XDR memory system is the bandwidth that it provides to the CELL processor. However, in the configuration illustrated in figure 9, the maximum of 4 DRAM devices means that the CELL processor is limited to 256 MB of memory, given that the highest capacity XDR DRAM device is currently 512 Mbits. Fortunately, XDR DRAM devices could in theory be reconfigured in such a way so that upwards of 36 XDR devices can be connected to the same 36 bit wide channel and provide 1 bit wide data bus each to the 36 bit wide point-to-point interconnect. In such a configuration, a two channel XDR memory can support upwards of 16 GB of ECC protected memory with 256 Mbit DRAM devices or 32 GB of ECC protected memory with 512 Mbit DRAM devices.
Unfortunately, rather than providing insights into the issue of the CELL processor's memory capacity, the statements above may have in fact contributed to the impression that the XDR memory system is currently constrained in some way. The truth of the matter is that the XDR DRAM devices themselves are capable of supporting the 72 device configuration that would allow each CELL processor to directly address 4 GB of ECC protected memory (given 512 Mbit XDR devices). However, in order to support the XDR DRAM device in such a configuration, specific support must be built into the XDR DRAM controller interface. To date, IBM has not released details on the memory controller interface indicating whether the current incarnation of the CELL processor can support a 72 DRAM device configuration in the XDR memory system, or a less amount, i.e. 36 DRAM devices. Fortunately, regardless of whether the current CELL processor can explicitly support the 72 DRAM device configuration in the XDR memory system, the ability to address 72 XDR DRAM devices would require at most a relatively minor design change for the CELL processor. As a result, even if a DRAM device-count limitation exists for the current incarnation of the CELL processor, future CELL processors can be easily designed to rectify that limitation. "
http://www.realworldtech.com/page.cfm?ArticleID=RWT022805234129
) I appended a note to that effect to my earlier post. Sorry, didn't mean to give the impression I'd deliberately ignored what you were saying.