In the DF article it mentions the following:
"Paired up with the eight AMD cores, we find a bespoke GPU-like "Compute" module, designed to ease the burden on certain operations - physics calculations are a good example of traditional CPU work that are often hived off to GPU cores."
If it really is "paired up" to the CPU, then it confirms a theory that Jeff_Rigby has had for several months.
Reading a 2010 patent by Sony (
http://www.google.com/patents/US20100312969) shows a chip that resembles Toshiba's "SpursEngine." In this patent, they detail a "Processing Element" (PE) that contains 1 PPU and 4 SPE's. In short, "half of a Cell."
The interesting thing about this patent, is that this PE can be hooked up to as many as one pleases. Hooking two together will create a "Cell equivalent." Now, one might ask, how much would that cost?" If integrated into the Jaguar APU, very little.
How? AMD Crossbar Switch.
The AMD solution currently rumored in the Orbis would have 4 "slots" on the crossbar to integrate their chips. As of current, Orbis has 8 Jaguar cores. There are 4 cores per Jaguar module. That means 2 slots take up the Crossbar, leaving 2 more opened. Just enough for two PE's. 8 Jaguar cores total with 2 PPU's and 8 SPU's.
Another possible configuration that Jeff mentions is 4 Steamroller cores (as 2 comes in each module), with the additional 2 PE's attached, but I digress.
In the patent there is this quote.
"The local PE bus can have, e.g., a conventional architecture or can be implemented as a packet-switched network."
This fits in-line perfectly with AMD's solution.
To further solidify this theory, we take a look at this quote:
"The PE is closely associated with a shared (main) memory through a high bandwidth memory connection. Although the memory preferably is a dynamic random access memory (DRAM), the memory could be implemented using other means, e.g. as a static random access memory (SRAM), a magnetic random access memory (MRAM), an optical memory, or a holographic memory, etc."
This allows any implementation of memory as the engineers see fit. Sony is no longer tied down to the use of XDR ram for these PE's. The GDDR5 bandwidth would satisfy the needs of the SPE's to make sure they aren't data starved.
What does this all mean?
This means several things:
Backwards compatibility is within reach, adding the two PE's will create an environment where they can emulate the Cell. The RSX can be emulated by the GPU, and the GDDR5 bandwidth is sufficient.
PS4 functions: As they mentioned in the article, it will take "GPU-like" functions. Why use the SPE's over conventional GPU cores? SPE's are much faster. They tackle GPU tasks in a CPU manner. Low core count, high speed. These functions include DSP, a feature that Sony has yet to address in the Orbis, physics tasks, and video processing (encoding/decoding). They can add all these features to the Orbis without having the GPU take a hit and sacrificing GPU tasks.