Stacking chips won't make it to either Wii U or 720. They haven't even finished development yet.
http://www.neogaf.com/forum/showpost.php?p=37578976&postcount=1549
Of note is a PDF from the April GSA global memory conference that shows 3D stacked and Ultra wide 3D stacked memory attached to logic in Game Console SOCs manufactured in 2013-2014.
In a AMD Fusion APU both the X86 CPU (in our rumored PS4 2 CPU cores and 400 GPU cores) and GP GPU can be used as a CPU. Combined they exceed the performance of 24-30 Cell SPUs and with other efficiencies discussed may be 113% more efficient at some tasks....that's equal to 60 SPUs or at some tasks 1200 times faster than a X86 processor alone. Far from weak this supports another model (CPU bound UE4) for games. (Example: bundled Ray tracing for lighting)
This is why I think rumors of Xbox 720 having 2 GPUs suggest Microsoft is also going to have a Fusion CPU-GPU plus second GPU. 4 X86 or 16 PPC or even 24 SPUs pale in comparison to a Fusion CPU-GPU.
Early leaks only mentioned one or both might go with AMD X86 processors and AMD GPUs. Without the Fusion of the two it does not make sense, PPUs + GPGPU or Cell + GPGPU makes more sense. My bad for not being up on AMD Fusion (HSA) & Fabric computing and what it brings to the table. Nvidia is combining an ARM CPU core with a GPGPU to offer the same Fusion and resulting efficiencies.
It's possible that IBM is providing a PPU + AMD GPU fusion chip, AMD has said this is possible for a ARM + AMD fusion or any CPU.
The OBAN mentioned as being used by IBM to produce the Xbox 720 can be what it was named for, a blank that is written on or rather a LARGE substrate with bumps upon which 3D stacked and 3D wafers are 2.5D attached. With proper software design tools and standards (IBM, Global Foundries and Samsung) for wafer sub assemblies it should be very easy to design custom SOC without large lead times. AMD has been working on this for 5 years.
According to the data gleaned from presentations by Samsung, Toshiba, AMD, and others, 3D IC assembly gives you the equivalent performance boost of 2 IC generations (assuming Dennard scaling wasn’t dead). Garrou then quoted AMD’s CTO Byran Black, who spoke at the Global Interposer Technology 2011 Workshop last month. AMD has been working on 3D IC assembly for more than five years but has intentionally not been talking about it. AMD’s 22nm Southbridge chips will probably be the last ones to be “impacted by scaling” said Black. AMD’s future belongs to partitioning of functions among chips that are process-optimized for the function (CPU, Cache, DRAM, GPU, analog, SSD) and then assembled as 3D or 2.5D stacks.
This is starting in 2012 with full production scheduled for 2013.
OBAN Japanese Coin
PPUs do not require a redesign to be used in a Fusion APU but Cell's ring cache will require a redesign, an older heterogeneous (PPU + SPUs) inside a modern Heterogeneous Fusion design with Fabric computing memory model creates issues.
Wikipedia on SOC a must read. Slightly out of date as it doesn't take into account 3D wafer stacking and it's impact on SOC.
Wikipedia article on FPGA (glue logic and configuration after testing a wafer, Security and more)
Applications of FPGAs include digital signal processing, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation, radio astronomy, metal detection and a growing range of other areas.
FPGA is the Programmable logic array mentioned by the Sony CTO for Coming Playstation Tech. The smaller the array the faster it can run (heat again) and
it also benefits from a HSA design where A CPU can load pre-configured designs into the FPGA dynamically as well as (same model with a HSA GPU) pre-fetch data using the branch prediction abilities of the CPU. (Both PPU and X86 have branch prediction abilities, a SPU does not. This may have been why a PPU was included in the Cell with SPUs.)