Unlikely, as full production isn't expected until some time in 2014, and even then, we're talking low volume high end products for another couple of years. 3D stacking isn't expected to hit consumer devices for another four or five years.
Could you cite because, while I've read that before I dismissed it as it does not make sense. Having information filtered through News types can slant what we understand.
3D wafer stacking is a third phase of 3D stacking that has economic benefits only if certain conditions are met; the first is
high volume. From my cite:
If there is enough demand for TSVs, GlobalFoundries also will bring up the technology in its Fab 1 in Dresden. A fab in Singapore will be used for additional capacity for 2.5-D chips using silicon interposers if demand for the process exceeds what the New York fab can handle. GlobalFoundries is also exploring use of TSVs for MEMS and other products.
This would seem to indicate as does IBM ramping up in the same time frame as part of the consortium that includes Global Foundries, IBM Foundries and Samsung Foundries that there is great demand and high volume expected.
As to volume, Game console chip sets will have massive volume.... 20 million plus. 3D stacking efficiencies are required for handhelds and in the past a premium paid for those efficiencies. 3D wafer stacking if volume is high enough can reduce handheld 3D stacked costs. Next generation game consoles require those same efficiencies to fit into a next generation power (both performance and energy/heat generated) envelope. The most economical method of providing those efficiencies is with 3D wafer stacking. (Sony CTO confirmed TSVs and stacking.)
Again from the cite:
"high-end graphics and CPUs will use it to link to DRAMs and memory stacks
A game console in the past used a high end CPU and GPU, for the Xbox360 and PS3 the CPU and GPU exceeded in different ways what was available on PCs. I and others expect the same this time. AMD has a roadmap for APUs with the next iteration a common memory pool with CPU and GPU on the same silicon. If they add memory, even if only the rumored 80meg eDRAM for the Durango, and use that instead of L3 or L2 cache a massive increase in performance is possible with no increase in power needed.
onQ123 said:
that don't make much sense because Jaguar is the low power CPU cores why would they replace the streamroller cores of the APU with Jaguar cores? & steamroller is not 32nm it's 28nm
http://hothardware.com/News/AMDs-Fin...s-Future-SoCs/
Reading the article you provided <grin> at the very end of the article <grin> gives us more to think about:
In desktop, the aging Piledriver will anchor the high-end until the end of the year. AMD's presentations from last year's Fusion summit indicate that the company's long-term goal is to integrate CPU and GPU until the graphics core essentially replaces the CPU's floating point units. It's possible that holding off on a new higher-end CPU core is AMD's way of delaying until a new GPU is ready to take on that role in the highest end of the market. Such a chip would conceivably debut in 2014, beyond the scope of these presentations.
The aging Piledriver will anchor the high-end until the end of the year then
Jaguar, which does not have a floating point unit which is not needed in game consoles but is the more advanced CPU and in 2014 AMD SOC.
"Such a chip would conceivably debut in 2014, beyond the scope of these presentations." So a SOC @ 28nm featuring a Jaguar CPU core and a new GPU that is fast enough to setup for time critical Floating point calculation that are normally handled by a dedicated FPU in a CPU as well as OpenCL.....combined with a second GPU (Graphics Core Next Southern Islands)....possible for the PS4?
Changing the description of the CPU-GPU package from APU to SOC even though it's even more of a APU...does that imply something like more than CPU and GPU are in the package? In the chart below, the center is what is rumored for PS4, two GPUs one in the APU with I/O and support chips in the APU and on the right a SOC instead of APU which would contain everything.
What does the term MODULAR SOC mean, 3D wafer = modular?
Modular SOC: "system-on-a-chip (SOC) design using reusable intellectual property (IP) cores has become a state-of-the-art implementation paradigm that has triggered novel business models based on IP core providers and system integrators. The IP cores are pre-designed and pre-verified by the core providers, how-ever SOC composition is the system integrators’ duty, who is also in charge of verification and manufacturing testing of the entire SOC, including the IP-protected internal cores.
So Modular SOC might be AMD IP Property (CPU, GPU, Support Chips) provided as modules (possibly 3D wafers with interconnect standards or just silicon for use with interposers) allowing for easier SOC modular construction. If Jaguar CPU we are very into the far right SOC future AMD designs.
“Bulldozer NG,” in this case, is Piledriver. Given that the company has canceled its original plan to move to a new platform and 10/20-core architecture in 2013, it’s possible that AMD’s server platforms will move directly from the configuration on the far left to the far right, SoC-style implementation. Historically, AMD’s desktop and server CPUs have been tightly linked as far as their CPU architectures are concerned — the fact that we don’t see third-generation CPU core anywhere in 2013 could mean that the company will move to a unified SoC for servers and high-end desktop in 2014.
The sweetvar26 post has, I think, issues;
1)
"They moved on to TSMC 28nm solution", TSMC is not Global Foundries and AMD letting their most advanced designs be made outside of the US, Outside of Global Foundries or IBM and to Taiwan's TSMC does not seem like good business. Also while TSMC is also to have 3D wafer stacking they are 100% in house with their own standards that do not match the Consortium of Global Foundries, IBM and Samsung.
2) If Jaguar is a 2014 design it's probably planned to be 20nm not 28nm (not as much of an issue but Global Foundries is gearing up for 28nm and 20nm 3D wafer stacking) and to utilize the most economical and HSA efficient SOC manufacturing processes which probably include 3D wafer stacking.
"So looks like there are 2 Jaguar CPC's (Core plus cache) with 4P/2MB. Clocked at 1.6Ghz(~1.25V)"
1) 1.25V is very high for a chip that's supposed to be efficient, lots of factors here but it seems high and even .01 volts difference is more efficient and I've read voltages are closer to 1.0V now with 3D gate planned for 14nm down to .6V.
2) 1.6 Ghz for the CPU sounds low for a desktop or game console but about right for a high end GPU so there might be confusion here.
The sweetvar26 post could be a troll but he did his homework and brought to our attention a possible.
