There are masses of whitepapers written about the subject.
But really, all you need is basic knowledge of the fabrication process and common sense. It's an indisputable fact.
Here's a really basic rundown.
Many many transistors make up a chip design. At any given process size, the more transistors you add to a design, the larger the total area of the design must be. This total area is called the DIE SIZE. Many many of these dies are manufactured at a time, on a silicon disc called a WAFER.
Here's what a wafer looks like:
(The dies printed on the edges of the wafer are partial, and are almost always discarded.) That is expected, and pre-calculated, and those partials do not count agains yield percentages as a defect.)
So, Here's an example of two identical 300mm wafers -- one with a die size of 15mm x 15mm:
...and the other with a die size of 20mm x 20mm:
At 100% yield (no errors) the wafer with the smaller 15mm x 15mm die would be capable of producing 256 Die Per Wafer (DPW) The same sized wafer used to fabricate a larger 20mm x 20mm die would only be capable of producing 140 DPW at 100%.
So that right there shows you a rather massive drop in yield per wafer simply due to increased die size.
...
That doesn't even take in the complexity problem, which is real, and significant. The more complicated parts you add to any machine, the more likely you are to have a failed part which in turn makes the machine fail.
Here's a PPT that explains some of these issues in more detail, like error distribution, which also has a terrible impact on the yield numbers of larger die size IC designs:
Powerpoint slides on die yield - Mercury.pr.erau.edu
