PaintTinJr
Member
And this seems to distil our different views, because even now - as has been the case of needing a special CU for the tempest engine in the PS5, or special Co-processors in the IO complex - the SPUs can subsume all those algorithms and more with custom software solutions. It was the ideal type of processor to send on a long space mission, where what you needed 5years after launch from a CU/ASIC of the time wasn't right anymore, and you needed DSP/GPU level performance with CPU versatility but at the expense of leaning on human programming ingenuity, which was gained in those flight years. So being a precursor to something less versatile and less general purpose isn't how I would describe the SPUs, even if I see what you are driving at.Stop misrepresenting what I say.
My point was that the SPE is a precursor to the modern CU. Sony even had the intention of having just the Cell to render graphics, before realizing the issues with yields.
Had Sony managed to get decent yields on the Cell, those SPEs would have been very similar in concept, to what the CUs we have today in a console SoC.
Your point that Cell led to Alder lake is complete non-sense. Cell was a dead end, that no one copied since.
And just because Alder Lake has one similarity in a very broad technical term, it does not mean it's related to Cell.
I'm not arguing that I can locate the resources from nearly 20years ago to prove I'm right(switch from http to https makes old info sparse), and clearly you don't want to accept that the Cell BE's EiB and flexIO were designed for hUMA operation, so we reach an impasse - I could try and point you to it being a ringbus with a token access mechanism, and why such a uncommon communication topology for the processor fits the Unified Memory Access paradigm like a glove, but you seem like, unless I can use a time-machine to get the pages I've read/seen to show you, you aren't interested...The page you posted has only one mention of hUMA and it refers to AMD's Heterogeneous Unified Memory Access. You continue to use the wrong term for Heterogeneous Computing.
I had hoped that me enlightening you on issues like the Cell BEs (RoadRunner) power efficiency and the nature of SPUs being autonomous after being kicked off, and SPUs - split across different Cell BE processor like they are in the Sony Zegos, fixstar boards, etc - being able to access unified XDR with equal priority via the EiB ringbus would have given me a bit good will from you, for you to trust that what I was recounting from the time was correct.. but sadly not it seems.